What you learn today
- Plan and split the base automation
- define interfaces
This week you planned, split up, described interfaces and prepared tests. Now that turns into the plan for the base automation – and the first chip that implements it.
The plan
| Subsystem | Code | Task |
|---|---|---|
| life support | LS | pressure, air, temperature |
| power | EN | batteries, generator, load shedding |
| production | PR | production orders |
| logistics | LG | stock and requests |
| central unit | Z | overview, alarms, distributing orders |
The interfaces
Every subsystem writes two Logic Memories, the central unit reads them:
| Memory | Writer | Content |
|---|---|---|
| “X_Status” | subsystem X | 0 fine, 1 warning, 2 fault |
| “X_Puls” | subsystem X | heartbeat, changes every tick |
| “X_Auftrag” | central unit | what the subsystem should do, different per system |
| “Z_Puls” | central unit | heartbeat of the central unit |
The orders are added in the coming weeks: load shedding stage for EN, piece count for PR, stock and request from LG.
Part 1: the core of the central unit
Today you build the part of the central unit without which nothing else works: it is alive, it notices whether the subsystems are alive, and it sums everything up in one number. For the start life support and power are enough.
- Heartbeat: “Z_Puls” counts up by one in every pass.
- Watchdog: if “LS_Puls” or “EN_Puls” does not change for 4 passes, the system counts as faulty – no matter what its status says.
- Failure: if a status or heartbeat memory is missing, the system counts as faulty as well.
- Overall state: the display “Basis” shows the worst status, green, yellow or red.
Milestones
- The central unit sends its heartbeat.
- The overall state is the worst reported status.
- A frozen heartbeat turns its system into a fault.
- A missing memory turns its system into a fault.
The watchdog only trusts the status while the heartbeat is alive. A hung chip often reports “0, all good” forever – that is exactly why the heartbeat exists.
Here the timeout and every check are still written out for two systems. Once PR and LG join, the chip gets long. Keep an eye on the characters, part 2 needs room.
Project task
Task
Build the core of the central unit according to the rules above: heartbeat “Z_Puls”, status and watchdog for LS and EN, overall state on “Basis” with colour.
Milestones
- Milestone 1: heartbeat of the central unit
- Milestone 2: overall state
- Milestone 3: frozen heartbeat
- Milestone 4: missing memory
Hints
Hint 1
Watchdog as in the control room: seq, add, mul, move, then sge tmp age TIMEOUT and select s tmp STOERUNG s.
Hint 2
Missing memory: add tmp s p is NaN as soon as one of the two is missing – then snan and select.
Hint 3
Total: move total s for the first system, max total total s for the second.
Quiz
2 questions. You pass from 60 % – the server does the grading.
Complete the day
- Passed all milestones of the project
- Passed the quiz with at least 60 %
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