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Day 356 of 365 · Expert · Month 12: Masterpieces

Project: base automation part 2

Project base automation, part 2: the finished central unit with a watchdog for all four subsystems, overview, alarm and order forwarding – checked by an acceptance test with five milestones.

Project 60 min Week 51

What you learn today

  • Build and connect subsystems
  • Tests
  • Acceptance

The last building block of the base automation. The subsystems are in place, the central unit can already do overview and alarm. Now it gets the two abilities that turn individual parts into one system: it watches whether every subsystem is alive, and it passes logistics' request on to production as an order. At the end there is an acceptance test – five milestones that prove everything fits together.

Watchdog for four systems

In part 1 every system had registers of its own for the last pulse and its age. For four systems that would be eight registers – too many. That is why the central unit puts the values into its own stack, as a small table:

AddressContent
0, 1LS: last pulse, age
2, 3EN: last pulse, age
4, 5PR: last pulse, age
6, 7LG: last pulse, age

The subroutine computes the address from the bit number (mul adr bit 2) and reads and writes with get and put on db – its own housing, so its own stack. sp stays untouched.

One pass, two ticks

Four systems with watchdog, display and colour together cost well over 128 instructions. Without intervention the chip would cut the tick off somewhere in the middle of the subroutine and continue in the next one – that would run, but nobody would know any more when which value applies. That is why the central unit splits its pass on purpose, as on day 305: a second yield after LS and EN ends the first tick, PR, LG and the rest follow in the second. A pass therefore takes one second, and TIMEOUT 4 means four seconds without a heartbeat.

Passing orders on

Logistics reports in “LG_Anforderung” what it needs. The central unit writes that number into “PR_Auftrag” – but only if power is healthy: status 0 and no watchdog alarm. Otherwise it writes 0, and production pauses. When power is back, the same number is in the order again, and because the number changes in the process (0 to 20), production accepts it anew.

The central unit's setup

DevicePrefabName
five LED displaysStructureConsoleLED5“Z_LS”, “Z_EN”, “Z_PR”, “Z_LG”, “Z_Basis”
klaxonStructureKlaxon“Z_Alarm”
buttonStructureLogicButton“Z_Quittung”
Logic MemoriesStructureLogicMemoryinterface from day 351

Acceptance

  1. Overview and overall state for all four subsystems.
  2. A frozen heartbeat turns its system into a fault and raises the alarm.
  3. New faults sound until acknowledged.
  4. Logistics' request is passed on, paused when power is unhealthy.
  5. A missing status memory is recognised as a fault.
Tip

Count the characters before you write comments. The central unit is the longest script of the year – the long version with all explanations belongs in the library, a short header is enough in the chip.

Warning

The central unit's stack now holds data. Whoever adds push and pop later has to make sure the stack does not grow over address 8 into the table. sp starts at 0 – exactly where LS stores its pulse.

Diagram

The stack with its pointer slot 0 10 slot 1 20 slot 2 30 slot 3 slot 4 sp = 3 next free slot push 40 pop r0 r0 = 30 last in, first out
The central unit's stack as a table: two places per subsystem for the last pulse and its age, address = 2 · bit number.

Project task

Task

Build the finished central unit according to the rules above. The interfaces are in the header of the starter code, the registers are assigned.

Milestones

  1. Milestone 1: overview and overall state
  2. Milestone 2: watchdog
  3. Milestone 3: alarm and acknowledgement
  4. Milestone 4: passing orders on
  5. Milestone 5: status memory missing

Hints

Hint 1

Extend the subroutine from day 355 by the watchdog: mul adr bit 2, get/put on db for pulse and age.

Hint 2

If status or pulse is missing, add tmp s p is NaN – then fault.

Hint 3

Forwarding: healthy power means EN_Status 0 and bit 1 not set in the fault word (ext tmp faults 1 1).

Quiz

3 questions. You pass from 60 % – the server does the grading.

Complete the day

  • Passed all milestones of the project
  • Passed the quiz with at least 60 %

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